This invention relates to an integrated circuit and more particularly to a protection circuit for an integrated circuit with high voltage input signals and improved oxide reliability.
Present complementary metal oxide semiconductor (CMOS) and bipolar-CMOS (BiCMOS) circuits employ electrostatic discharge protection (ESD) circuits to protect against electrostatic discharge due to ordinary human and machine handling. This electrostatic discharge occurs when the semiconductor circuit contacts an object that is charged to a substantially different electrostatic potential of typically several thousand volts. The contact produces a short-duration, high-current transient in the semiconductor circuit. This high current transient may damage the semiconductor circuit through joule heating. Furthermore, high voltage developed across internal components of the semiconductor circuit may damage MOS transistor gate oxide.
Sensitivity of the semiconductor circuit is determined by various test methods. A typical test circuit used to determine sensitivity of the semiconductor circuit to human handling includes a capacitor and resistor that emulate a human body resistor-capacitor (RC) time constant. This test circuit is frequently referred to as a human body model (HBM) test. The capacitor is preferably 100 pF, and the resistor is preferably 1500 xcexa9, thereby providing a 150-nanosecond time constant. A semiconductor device is connected to the test circuit at a predetermined external terminal for a selected test pin combination. In operation, the capacitor is initially charged to a predetermined stress voltage and discharged through the resistor and the semiconductor device. A post stress current-voltage measurement determines whether the semiconductor device is damaged. Although this test effectively emulates electrostatic discharge from a human body, it fails to comprehend other common forms of electrostatic discharge.
A charged-device ESD test is another common test method for testing semiconductor device sensitivity. This method is typically used to determine sensitivity of the semiconductor circuit to ESD under automated manufacturing conditions. The test circuit includes a stress voltage supply connected in series with a current limiting resistor. The semiconductor device forms a capacitor above a ground plane that is typically 1-2 pF. A low impedance conductor forms a discharge path having an RC time constant typically two orders of magnitude less than a human body model ESD tester. In operation, the semiconductor device is initially charged with respect to the ground plane to a predetermined stress voltage. The semiconductor device is then discharged at a selected terminal through the low impedance conductor. This connection produces a high-voltage, high-current discharge in which a magnitude of the initial voltage across the semiconductor device approaches that of the initial stress voltage.
A particular problem of protection circuit design arises on circuits with multiple voltage supply lines such as Vss. High current during ESD stress develops high voltage across the parasitic resistance of these voltage supply lines. These resulting high voltages vary with the ESD stress pin combination and induce complex stress current paths within the circuit. These complex current paths may cause failures in the internal circuit that are difficult to anticipate and to detect. Moreover, conventional protection schemes may be ineffective in preventing failure from these complex current paths, since they concern stress current flow in an intended protection circuit rather than in an internal circuit.
Referring to FIG. 1, there is a plot of HBM failure voltages for semiconductor device pins 1-141 with respect to Vss. The semiconductor device pins are generally arrayed around the perimeter of the semiconductor device in the order of the plot. The failure voltages are determined by application of ESD stress voltage in increasing increments for each pin combination until the semiconductor device fails. The semiconductor device includes several types of standard cells as indicated in the legend. Each type of standard cell has substantially the same physical layout, although it may be flipped or rotated in various placements around the perimeter of the semiconductor device as is well known to those of ordinary skill in the art. The standard cell types include input/output (I/O) cells (FIG. 2A), Output cells (FIG. 2B), Input 2 type cells (FIG. 2C) and Input 6 type cells (FIG. 2D). A wide variation of failure voltages for a single standard cell is evident from the plot. For 15 example, an output cell at pin 13 fails at 2000 volts at region 110. The same output cells at pins 14 and 15 in region 112 fail above 3000 volts. An output cell at pin 21, however, fails above 5000 volts. Similarly, an I/O cell at pin 67 fails at 2500 volts while the same I/O cell fails at 5000 volts at pin 79 in region 120. In each case, the failure voltage increases for pins close to a Vss pin and decreases for pins that are remote from a Vss pin. An Output cell at region 114 and adjacent to Vss pin 102 has a much higher failure voltage than pin voltages plotted at either region 110 or region 116. The same pattern applies to the I/O cell plotted at region 120 compared to I/O cells plotted at regions 118 and 122. Thus, increasing parasitic resistance of Vss supply lines significantly degrades respective failure voltages of like cells as the distance from Vss pins increases.
These problems are resolved by a semiconductor device with a common supply voltage terminal. A plurality of standard cells, each having a plurality of leads is connected to the common supply terminal. A plurality of connecting leads corresponding to respective standard cells is coupled between at least two leads of the plurality of leads.
The present invention eliminates premature semiconductor device failure due to high voltage signals.